Design and Implementation of a Real-time Traffic Light Control

Traffic lights help people to move properly in the junctions by stopping the route for one side and allowing the other. But most of the traffic lights have fixed time controller which makes the vehicles to stop for a long time during peak hours. Because of this, traffic congestion is increased during peak hours. Sometimes traffic police placed in the congestion areas to manage the traffic this shows the ineffectiveness of the system. While for smaller roads sensors are used to control the traffic autonomously.

In this VLSI design project, we will design an FPGA based traffic light controller system which reduces the waiting time of the drivers during peak hours. VHDL is used to design FPGA because with VHDL you can simulate the operation of digital circuits from an easy one to complex gates.

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Quartus II software is used to design the Traffic light controller based on VHDL and with the help of Altera FLEX 10K chip, the hardware is created.

FPGA - Field Programmable Gate Array is an IC (Integrated Circuit) which can be modified by the customer or designer based on their requirement after manufacturing. In the electronics industry, the components are manufactured based on their standards and protocols which makes it difficult for the users to configure it according to their needs. This created a requirement for new hardware which can be configured by the user or designer.

FPGA contains programmable logic blocks and interconnection circuits which can be modified based on the requirement after manufacturing. FPGA is cheaper for small scale requirements when compared to ASIC (Application-specific Integrated circuit) which is suitable for large scale production.

Project Implementation

Road Structure - A complex road is identified and the structure is recreated and the timing for the lights are fixed. The timing is created wisely to avoid accidents in the junctions. In our case, there are six traffics, TR1, TR2, TR3, TR4, TR5 and TR6. TR1 and TR2 is the main road for the first junction. TR3 and TR4 is the main road for the second junction. TR5 and TR6 are the smaller roads.

VHDL model of the controller is created. It consists of CLOCK, RESET, PEAK, OUTPUT, SENSOR 1 AND SENSOR 2.

Timing simulation is done to verify the result of the design. Following are the peak hours set for this project 7-9, 12-14 and 17-19. The simulation is performed for various scenarios:

• First cycle - TR1 and TR6 are green and others are red. TR1 and TR6 will change to amber after 32s and stays for 4s then red for 2s.
• Second cycle - TR2 and TR4 starts with green for 32s then amber for 4s at last red for 2s.
• Third cycle - TR3 and TR5 (narrow roads) turn green for 16s followed by amber for 4s and red for 2s.

After this first cycle is repeated again. Now the simulation is performed successfully using Altera FELIX10K chip. The major advantage of this design over the conventional system is, it reduces the waiting time of the drivers during the off-peak hour.

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• Verilog
• Xilinx

• Embedded systems
• VLSI design
• VHDL
• Robotics

Design and Implementation of a Real-time Traffic Light Control