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Instruction set architecture is an integral part of a processor, which is necessary for creating machine level programs to perform any mathematical or logical operations. This acts as an interface between hardware & software and make the processor respond to commands like execution, creation, deletion etc. given by the user.

The performance of a processor solely depends upon the instruction set architecture designed in it. We know both software and hardware are needed for proper functioning of a processor, but there is always a debate about which should play a major role.

For example, the hardware part of Intel is named as Complex Instruction Set Computer (CISC) and Apple named their hardware as Reduced Instruction Set Computer (RISC)

Intel believes that hardware should play a major role than the software and built their processor on CISC. Whereas Apple bet is on software rather than hardware and built their processor on RISC.

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CISC Architecture:

CISC based processors can perform numerous low-level operations like loading a value from memory, performing arithmetic operations and storing a value in memory etc. simultaneously with single instructions.

In the past, to calculate complex arithmetic operations, compilers had to create long sequence of machine code. To avoid this, researchers had built an architecture which can access memory less frequently to reduce the burden on the compiler. CISC achieves this by directly using the memory instead of a register file. For this, CISC is made with micro-programmed control and cache memory.

This architecture uses cache memory for holding both data and instructions. Instructions in CISC are executed by a micro program which has sequence of micro instructions.

Advantages of CISC Architecture:

  1. Since the micro program instruction sets can be written to match the high level language constructs, the compiler need not be that complicated.
  2. Also as the CISC architecture uses general purpose hardware to carry out the execution commands, it is very easy to add new commands to the chip without changing its architecture.
  3. CISC Architecture uses the main memory efficiently since the complexity design allows usage of lesser number of instructions to execute commands
  4. In CISC, it is easier to implement micro-programming and is relatively less expensive too

Disadvantages of CISC Architecture:

  1. The overall execution speed is relatively less due to the slower clock speed
  2. Since it is designed to perform many functions, the hardware design is complex
  3. The new version of CISC processors contain early generation processors in their subsets. So, the chip hardware and instruction became complex with each new version of the processor.


  1. IBM 370/168
  2. Intel 80486
  3. VAX 11/780
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RISC Architecture:

RISC processors use simple commands which are then divided into several instructions to achieve low-level operation within a single clock cycle. This processor is designed to perform simple orders and act fast.

Especially in RISC architecture, the instruction set of the processor is simplified to reduce the execution time. It uses pipeline technique for execution of any instruction. In RISC architecture, the instruction set of processors is simplified to reduce the execution time. It uses small and highly optimized set of instructions which are generally used to register operations.

The speed of execution can be increased by using more small number of instructions. This uses pipeline technique to execute any instruction. The pipelining technique allows the processor to work on different steps of instruction like fetch, decode and execute instructions at the same time.

Advantages of RISC Architecture:

  1. It is much faster compared to the CISC processors because of its simplified instruction set
  2. RISC processors can be designed much faster than CISC processors due to its simple architecture
  3. The execution of instructions is high for this processor due to the usage of many registers to hold and pass the instructions
  4. This architecture uses less chip space due to reduced instruction set. This makes place to embed extra functions like floating point arithmetic units or memory management units on to the chip.
  5. The per-chip cost is reduced by this architecture since it uses smaller chips consisting of more components on a single silicon wafer

Disadvantages of RISC Architecture:

  1. These processors need very fast memory systems to feed numerous instructions. So, a large memory cache is provided on the chip.
  2. The performance of a RISC processor depends on the code that is being executed. Any discrepancies in the first instruction would make the compiler to do poor job on scheduling the following instructions.


  1. AVR
  2. ARM
  3. PIC
  4. PA-RISC

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