Instruction set architecture is an integral part of a processor, which is necessary for creating machine level programs to perform any mathematical or logical operations. This acts as an interface between hardware & software and make the processor respond to commands like execution, creation, deletion etc. given by the user.
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The performance of a processor solely depends upon the instruction set architecture designed in it. We know both software and hardware are needed for proper functioning of a processor, but there is always a debate about which should play a major role.
For example, the hardware part of Intel is named as Complex Instruction Set Computer (CISC) and Apple named their hardware as Reduced Instruction Set Computer (RISC)
Intel believes that hardware should play a major role than the software and built their processor on CISC. Whereas Apple bet is on software rather than hardware and built their processor on RISC.
CISC based processors can perform numerous low-level operations like loading a value from memory, performing arithmetic operations and storing a value in memory etc. simultaneously with single instructions.
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In the past, to calculate complex arithmetic operations, compilers had to create long sequence of machine code. To avoid this, researchers had built an architecture which can access memory less frequently to reduce the burden on the compiler. CISC achieves this by directly using the memory instead of a register file. For this, CISC is made with micro-programmed control and cache memory.
This architecture uses cache memory for holding both data and instructions. Instructions in CISC are executed by a micro program which has sequence of micro instructions.
Advantages of CISC Architecture:
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Disadvantages of CISC Architecture:
RISC processors use simple commands which are then divided into several instructions to achieve low-level operation within a single clock cycle. This processor is designed to perform simple orders and act fast.
Especially in RISC architecture, the instruction set of the processor is simplified to reduce the execution time. It uses pipeline technique for execution of any instruction. In RISC architecture, the instruction set of processors is simplified to reduce the execution time. It uses small and highly optimized set of instructions which are generally used to register operations.
The speed of execution can be increased by using more small number of instructions. This uses pipeline technique to execute any instruction. The pipelining technique allows the processor to work on different steps of instruction like fetch, decode and execute instructions at the same time.
Advantages of RISC Architecture:
Disadvantages of RISC Architecture:
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